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Duplication Burden
Dual-core lockstep can impose significant area, power, memory, verification, and integration overhead for large CPUs, GPUs, DSPs, and accelerators.
VEGASAFE™
Runtime Functional Safety Intelligence for Modern SoCs
VegaSafe™ provides execution-coupled functional safety intelligence that combines runtime silicon observability with structural diagnostic coverage to improve fault detection, latent-fault awareness, and common-cause-failure visibility. It offers an evolutionary path to strengthen conventional dual-lockstep architectures and a transformational path toward single-core lockstep-equivalent diagnostic confidence with lower duplication overhead across heterogeneous SoCs.
The Challenge
Classical Safety Architectures Are Becoming Too Costly and Too Fragmented
Modern AI, automotive, robotics, industrial, aerospace, and mission-critical SoCs contain large heterogeneous compute fabrics where safety concerns extend beyond logical comparison. Voltage droop, timing stress, thermal behavior, aging, clock disturbance, latent faults, and shared infrastructure effects can create failures that are difficult to address with isolated safety mechanisms.
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Common-Cause Failures
Shared voltage, clock, thermal, interconnect, and aging conditions can affect redundant logic in correlated ways that simple comparison may not fully expose.
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Latent Fault Visibility
Safety architectures need stronger runtime awareness of dormant or accumulated faults without relying only on intrusive shutdown-based diagnostics.
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Fragmented Safety Flows
Structural test, runtime diagnostics, safety mechanisms, telemetry, and lifecycle monitoring are often developed as separate flows with limited coordination.
Our Solution
Execution-Coupled Runtime Safety Control
VegaSafe™ introduces runtime functional safety intelligence based on direct observation of silicon behavior while the SoC is operating under real workloads.
Instead of treating safety only as a static redundancy problem, VegaSafe combines runtime observability, structural diagnostic intent, margin awareness, anomaly detection, and coordinated safety response into a unified framework.
VegaSafe turns functional safety from a duplication-heavy architecture into a runtime silicon integrity problem.
Architecture Overview
Runtime Functional Safety Architecture
VegaSafe combines execution-coupled observability, structural diagnostic intelligence, runtime integrity monitoring, and coordinated safety response into a scalable safety framework for modern SoCs.
The architecture is designed to strengthen existing lockstep designs while also enabling lower-overhead safety paths for large heterogeneous compute blocks where full duplication can be impractical.
- Runtime structural and timing-integrity observation
- Common-cause awareness across voltage, clock, thermal, and aging effects
- Latent-fault support without heavy shutdown-based diagnostics
- Integration with safety monitors, PMU, telemetry, and SoC control
- Coverage-oriented runtime diagnostic intent
- Support for both lockstep enhancement and single-core safety paths
Safety Architecture Paths
Two Practical Paths for Modern Safety-Critical SoCs
VegaSafe can be applied as an enhancement to existing redundant architectures or as a lower-overhead safety foundation for compute blocks where duplication is too costly.
Path 01
Enhance Dual-Core Lockstep
VegaSafe strengthens conventional lockstep by adding runtime observability into common-cause effects, timing-correlated failures, latent faults, and shared infrastructure disturbances that simple comparator-based schemes may not fully characterize.
- Common-cause awareness
- Runtime latent-fault support
- Timing and voltage anomaly visibility
- Stronger safety-case evidence
Path 02
Enable Single-Core Safety Equivalence
VegaSafe enables a path toward lockstep-class diagnostic confidence with lower duplication overhead by applying runtime structural diagnostics and execution-coupled integrity monitoring directly within the functional execution fabric.
- Reduced area and power burden
- Better fit for large XPUs
- Runtime diagnostic coverage support
- Scalable safety for heterogeneous SoCs
Key Capabilities
What VegaSafe Enables
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Runtime Integrity Awareness
Observes structural and timing behavior during operation rather than relying only on offline or periodic diagnostics.
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Common-Cause Visibility
Improves awareness of voltage, clock, thermal, aging, and infrastructure effects that can impact redundant safety elements together.
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Latent-Fault Support
Supports lifecycle-aware detection of dormant or accumulated faults without requiring intrusive downtime-heavy test strategies.
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Lockstep Enhancement
Adds execution-coupled safety visibility to conventional lockstep architectures for stronger runtime confidence.
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Single-Core Safety Path
Enables lower-overhead safety approaches for large CPUs, GPUs, DSPs, NPUs, and accelerators where full duplication is expensive.
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Unified Safety Telemetry
Provides runtime safety intelligence that can feed system control, RAS, SLM, firmware, and safety-management layers.
System-Level Benefits
Safety Impact Across Silicon and Platform Architecture
Reduced Safety Overhead
Helps reduce duplication-driven area, power, memory, and integration cost for large compute blocks.
Stronger Fault Awareness
Extends safety visibility into timing stress, runtime anomalies, and structural behavior inside the functional fabric.
Improved Common-Cause Coverage
Supports awareness of correlated voltage, clock, thermal, aging, and shared-infrastructure effects.
Better Fit for Heterogeneous SoCs
Enables safety strategies for XPUs and accelerators that are difficult or expensive to duplicate.
Lifecycle Safety Confidence
Provides runtime evidence as silicon ages and as workload, environment, and operating conditions change.
Unified Safety Foundation
Connects structural diagnostics, runtime telemetry, functional safety, reliability, and system response into one framework.
Standards & Ecosystem Fit
Built for Safety-Critical Semiconductor Platforms
VegaSafe is designed to support standards-aligned safety architectures across automotive, industrial, robotics, aerospace, avionics, and mission-critical compute platforms.
ISO 26262 / ASIL-D
IEC 61508
ISO 13849
DO-254
DO-178C Context
SPFM / LFM Support
Common-Cause Awareness
RAS / SLM Telemetry
Automotive / Industrial / Aerospace
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Ready to Rethink Runtime Functional Safety?
Explore how VegaSafe™ enables execution-coupled safety intelligence for modern SoCs operating under real workload, voltage, thermal, aging, and mission-critical conditions.